1. Field of the Invention
The present invention relates to a USB (Universal Serial Bus) test circuit for testing a USB function, and particularly to a USB test circuit for use in a USB device such as a system LSI (Large Scale Integration) with a USB function for testing the USB function.
2. Description of the Background Art
The conventional system LSI operates using a built-in central processing unit (CPU). The CPU connects to via a system bus to other circuits to perform the functions of the circuits. Some of the system LSIs include a USB device controller connected to the system bus and a USB physical layer (PHY) connected to the controller, thus providing a USB function. The CPU can read and write data to registers included in the USB device controller.
The USB PHY layer connects, for example, via a USB 2.0 Transceiver Macrocell Interface (UTMI) to the USB device controller, and via a USB interface (I/F) to an external device. The USB PHY layer has a UTMI I/F controller block that controls the UTMI interface, and transmits and receives over the USB interface a DP/DM (Differential data Plus/Differential data Minus) signal.
The USB device controller serves to control the USB protocol. The USB device controller connects via a system bus interface to the system bus and via the UTMI interface to the USB PHY layer. The controller has the UTMI I/F controller block that controls the UTMI interface. The controller also has a protocol identifier (PID) decode block, a high-speed test packet generation block, and an acknowledgment (ACK) packet generation block.
The PID decode block functions as determining the type of a packet received on the DP/DM signal via the USB interface. The PID decode block decodes, for example, a received packet to detect a PID, and uses the PID to determine the packet type.
The high-speed test packet generation block serves to generate, when the system LSI operates in a test mode such as the compliance test mode, a test packet of the USB function in the high speed mode. In the high speed mode, when the USB device controller receives a request for the test packet generation from the USB interface, the high-speed test packet generation block generates a test packet and supplies it to the USB PHY layer. The USB PHY layer outputs the test packet via the USB interface on the DP/DM signal.
The ACK packet generation block functions as generating an ACK packet when the system LSI receives a packet via the USB interface and in response an ACK packet needs to be returned. The ACK packet generation block supplies the generated ACK packet to the USB PHY layer, which outputs the ACK packet on the DP/DM signal via the USB interface.
When the system LSI performs the USB compliance test to thereby measure the signal quality of the USB in the full speed/low speed mode, a reception of plural packets such as a SETUP packet or a DATA packet which are not to be measured by the USB device controller causes the controller to generate an ACK packet, which is to be measured for testing the signal quality, and to supply the ACK packet to the USB PHY layer, which in turn outputs the packet on a DP/DM signal.
When the system LSI performs the USB compliance test to thereby measure the signal quality of the USB in the high speed mode, a reception of plural packets that are not to be measured by the USB device controller causes to generate a test packet that is to be measured for testing the signal quality, and to supply the test packet to the USB PHY layer, which in turn outputs the packet on a DP/DM signal.
U.S. Pat. No. 6,880,027 B1 to Oguro discloses a USB function evaluation system that works as follows. The test pattern sent to the USB function is temporarily stored in an IN token storage memory. The data returned from the USB function is determined by a packet type determination circuit. If the returned data is the NAK type, the stored IN token is re-sent. If the returned data is the DATA type or STALL type, the held IN token is discarded. The time for the DATA packet to be ready for the return can thus be unconsidered during programming. The design efficiency of the test pattern can therefore be improved.
Japanese patent laid-open publication No. 2001-245017 discloses a USB simulation system that is configured as follows. The simulation system has storage media that stores test items and instructions for a simulation. A transaction manager manages the test items for each transaction. A received data determination portion determinates a reply signal. The determination result is used to create a branch for further processes. Test items to be performed or data to be transmitted in the next transaction can thus be selected.
The conventional system LSIs with the USB function have a problem, however, with the USB test as follows. When performing the USB test and allowing the USB PHY layer to output a packet for observation of the signal quality, the system LSIs need to transmit a plurality of redundant packets not directly related to the measurement to the USB device controller. More time is therefore required for the signal quality observation. For example, the system taught by Oguro or the Japanese '017 publication transmits an ACK signal in response to a packet not to be measured such as a SETUP packet or DATA packet received.
The SETUP packet is usually a 32-bit packet that has an 8-bit SYNC, an 8-bit PID, a 7-bit ADDR, a 4-bit ENDP, and a 5-bit CRC5 field. The DATA packet is usually a 96-bit packet that has an 8-bit SYNC, an 8-bit PID, a 64-bit DATA, and a 16-bit CRC16 field. When, therefore, the system LSIs are mass-produced and shipped after a test that starts on receipt of the packets not to be measured, the test will take a long time to receive those packets and the lengthy test time will significantly affect the LSI costs.
In the conventional USB devices with the USB test function, a plurality of test patterns have to be produced even for packets not to be measured, thereby needing much manpower for producing such test patterns and much time for debugging.